Laminating a magnetic core is a well know technique that reduces the adverse effect of eddy currents on the performance of inductors and transformers. While being relatively straightforward to implement in the macro world, fabricating laminations presents challenges in the case of micro-fabricated and on-chip inductor structures.
One of the approaches to fabricating on-chip inductors is to deposit laminations horizontally, layer by layer, separated by thin dielectric films. Those skilled in the art will appreciate that this approach requires multiple deposition steps to build sufficient volume of magnetic material, which makes this approach prohibitively expensive. Therefore, all practical solutions of this type to date are limited to one or two laminations. See, for example, S. C. O. Mathuna et al., “Magnetics on Silicon: An Enabling Technology for Power Supply on Chip,” IEEE Transactions on Power Electronics, Vol. 20, No. 3, May 2005, pp. 585-592. In this case, the performance of the inductor is limited because of the low total amount of magnetic material.
Alternatively, laminations can be built vertically utilizing photolithography. These solutions are known for very thin film inductors that do not receive practical exposure for the same reasons set forth above with respect to the horizontal lamination approach. See, for example, D. S. Gardner et al., “Integrated On-Chip Inductors With Magnetic Films,” IEEE Transactions on Magnetics, Vol. 43, No. 6, June 2007. pp. 2615-2617.
Another type of known micro-fabricated inductor utilizes vertical laminations that are large (i.e., hundreds of microns in cross-section), which does little to help reduce eddy currents. See, for example, P. Galle et al., “Ultra-Compact Power Conversion Based on a CMOPS-Compatible Microfabricated Power Inductor with Minimized Core Losses,” 2007 Electronic Components Technology Conference, pp. 1889-1894. In addition, inductors of this type are prohibitively large.
Commonly-assigned and co-pending U.S. patent application Ser. No. 12/082,209, filed on Apr. 9, 2008, by Smeys et al., and titled “MEMS Power Inductor and Method of Forming the MEMS Power Inductor,” discloses a scalable MEMS inductor formed on the top surface of a semiconductor die. The disclosed thick film magnetic inductors have vertically designed laminations that are built inside thick photoresistive films, thereby providing large volumes of magnetic material while the cross-sectional dimension of about 10 μm helps to make this high performance device within a few square millimeters. The aspect ratio of the lamination cross-section is in the range of 3:1 to 4:1, which reduces eddy currents. (See also, U.S. Pat. No. 7,705,411, which issued to Smeys et al. on Apr. 27, 2010, and is hereby incorporated by reference herein in its entirety to provide background information regarding the present invention.)